The present invention relates to oversampled data converters generally and, more particularly, to a method and/or architecture for providing hysteresis in an oversampled data converter.
Referring to FIG. 1, a block diagram illustrating a 1-bit first order Sigma-Delta D/A converter 10 is shown. The converter 10 has an adder 12, an integrator 14, a quantizer 16 and a feedback network 18. Low-bitrate data converters use the low-resolution quantizer 16 at a high sampling rate. The maximum signal-to-error ratio for the converter 10 is:             (              S        E            )        ⁢          xe2x80x83        ⁢          (      dB      )        =            6.02      ⁢              (                  N          +                      1.5            ⁢            L                          )              -    3.41  
(where N=quantization bits, and L=octaves of oversampling).
Increasing the octaves of oversampling (L) will improve performance, with some limitations. For example, doubling the output frequency will double the power consumption at the output pin(s). However, the output pin(s) can have non-linearities.
Referring to FIG. 2a, a diagram illustrating a CMOS output buffer driver 20 is shown. The CMOS driver 20 has a NMOS transistor M1 and a PMOS transistor M2. If the NMOS transistor M1 has more drive than the PMOS transistor M2, the signal OUTPUT will not be balanced. Such an unbalanced output is shown in block 22 of FIG. 2b. Each high pulse is shortened (i.e., the portions 24, 26 and 28) and each low pulse is lengthened (i.e., the portions 30 and 32). The distortion of the signal OUTPUT will add noise to the system.
Increasing the oversampling ratio of the data converter 10 will not reduce the effects of a nonlinearity in the output driver 20 of a D/A converter (or the input comparator of an A/D converter). Under some conditions, increasing the oversampling rate can actually reduce system performance by increasing the frequency of transitions. Increasing the number of transitions at the output will increase the effect of the non-linearities.
A system with reasonable performance and fewer transitions at the output pin(s) would be desirable.
The present invention concerns an apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate an intermediate signal in response to an input signal and a first feedback signal. The second circuit may be configured to generate an output signal in response to the intermediate signal and a second feedback signal. The third circuit may be configured to generate the first feedback signal and the second feedback signal in response to the output signal.
The objects, features and advantages of the present invention include providing an apparatus an method for implementing hysteresis in an oversampled data converter that may (i) reduce the number of transitions at the output, (ii) reduce output power, (iii) reduce effects of nonlinearities associated with transitions, and/or (iv) correct unknown nonlinearities due to fluctuation in process or temperature.